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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">CCSIDR, Current Cache Size ID Register</h1><p>The CCSIDR characteristics are:</p><h2>Purpose</h2>
        <p>Provides information about the architecture of the currently selected cache.</p>

      
        <p>When <span class="xref">FEAT_CCIDX</span> is implemented, this register is used in conjunction with <a href="AArch32-ccsidr2.html">CCSIDR2</a>.</p>
      <h2>Configuration</h2><p>AArch32 System register CCSIDR bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-ccsidr_el1.html">CCSIDR_EL1[31:0]</a>.</p><p>This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to CCSIDR are <span class="arm-defined-word">UNDEFINED</span>.</p>
        <p>The implementation includes one CCSIDR for each cache that it can access. <a href="AArch32-csselr.html">CSSELR</a> and the Security state select which Cache Size ID Register is accessible.</p>
      <h2>Attributes</h2>
        <p>CCSIDR is a 32-bit register.</p>
      <h2>Field descriptions</h2><h3>When FEAT_CCIDX is implemented:</h3><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="8"><a href="#fieldset_0-31_24">RES0</a></td><td class="lr" colspan="21"><a href="#fieldset_0-23_3">Associativity</a></td><td class="lr" colspan="3"><a href="#fieldset_0-2_0">LineSize</a></td></tr></tbody></table><div class="text_before_fields">
    <div class="note"><span class="note-header">Note</span>
      <p>The parameters NumSets, Associativity, and LineSize in these registers define the architecturally visible parameters that are required for the cache maintenance by Set/Way instructions. They are not guaranteed to represent the actual microarchitectural features of a design. You cannot make any inference about the actual sizes of caches based on these parameters.</p>
    </div>
  </div><h4 id="fieldset_0-31_24">Bits [31:24]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-23_3">Associativity, bits [23:3]</h4><div class="field">
      <p>(Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2.</p>
    </div><h4 id="fieldset_0-2_0">LineSize, bits [2:0]</h4><div class="field"><p>(Log<sub>2</sub>(Number of bytes in cache line)) - 4. For example:</p>
<p>For a line length of 16 bytes: Log<sub>2</sub>(16) = 4, LineSize entry = 0. This is the minimum line length.</p>
<p>For a line length of 32 bytes: Log<sub>2</sub>(32) = 5, LineSize entry = 1.</p>
<div class="note"><span class="note-header">Note</span><p>The C++ 17 specification has two defined parameters relating to the granularity of memory that does not interfere. For generic software and tools, Arm will set the hardware_destructive_interference_size parameter to 256 bytes and the hardware_constructive_interference_size parameter to 64 bytes.</p></div></div><h3>Otherwise:</h3><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_1-31_28">UNKNOWN</a></td><td class="lr" colspan="15"><a href="#fieldset_1-27_13">NumSets</a></td><td class="lr" colspan="10"><a href="#fieldset_1-12_3">Associativity</a></td><td class="lr" colspan="3"><a href="#fieldset_1-2_0">LineSize</a></td></tr></tbody></table><div class="text_before_fields">
    <div class="note"><span class="note-header">Note</span>
      <p>The parameters NumSets, Associativity, and LineSize in these registers define the architecturally visible parameters that are required for the cache maintenance by Set/Way instructions. They are not guaranteed to represent the actual microarchitectural features of a design. You cannot make any inference about the actual sizes of caches based on these parameters.</p>
    </div>
  </div><h4 id="fieldset_1-31_28">Bits [31:28]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">UNKNOWN</span>.</p>
    </div><h4 id="fieldset_1-27_13">NumSets, bits [27:13]</h4><div class="field">
      <p>(Number of sets in cache) - 1, therefore a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2.</p>
    </div><h4 id="fieldset_1-12_3">Associativity, bits [12:3]</h4><div class="field">
      <p>(Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2.</p>
    </div><h4 id="fieldset_1-2_0">LineSize, bits [2:0]</h4><div class="field"><p>(Log<sub>2</sub>(Number of bytes in cache line)) - 4. For example:</p>
<p>For a line length of 16 bytes: Log<sub>2</sub>(16) = 4, LineSize entry = 0. This is the minimum line length.</p>
<p>For a line length of 32 bytes: Log<sub>2</sub>(32) = 5, LineSize entry = 1.</p>
<div class="note"><span class="note-header">Note</span><p>The C++ 17 specification has two defined parameters relating to the granularity of memory that does not interfere. For generic software and tools, Arm will set the hardware_destructive_interference_size parameter to 256 bytes and the hardware_constructive_interference_size parameter to 64 bytes.</p></div></div><div class="access_mechanisms"><h2>Accessing CCSIDR</h2>
        <p>If <a href="AArch32-csselr.html">CSSELR</a>.{Level, InD} is programmed to a cache level that is not implemented, then on a read of the CCSIDR the behavior is <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span>, and can be one of the following:</p>

      
        <ul>
<li>The CCSIDR read is treated as NOP.
</li><li>The CCSIDR read is <span class="arm-defined-word">UNDEFINED</span>.
</li><li>The CCSIDR read returns an <span class="arm-defined-word">UNKNOWN</span> value.
</li></ul>
      <p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b001</td><td>0b0000</td><td>0b0000</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T0 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T0 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TID2 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TID4 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TID2 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR2.TID4 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        R[t] = CCSIDR;
elsif PSTATE.EL == EL2 then
    R[t] = CCSIDR;
elsif PSTATE.EL == EL3 then
    R[t] = CCSIDR;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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